With the continuous reduction of semiconductor device size in scale, there is the problem that the threshold voltage falls with the reduction in the channel length, namely, a short channel effect occurs in the semiconductor device. In order to suppress such short channel effect, a new structure of Fin Field Effect Transistor (Fin FET) is used in the industry, that is, a plurality of parallel silicon Fins perpendicular to the SOI substrate are formed in a thin silicon layer at the top of the substrate, a channel region is formed at the middle of the silicon Fins, and source and drain regions are formed at the two ends of the silicon Fins, while a control gate is distributed across the plurality of silicon Fins.
However, due to the limitation of the etching process, the silicon Fins in the prior art have rectangular cross-sections, and accordingly, the control gate is conformal thereto, so the ratio of surface area to volume is small and the gate control capability is weak, and for a device whose channel is continuously reduced, the capability of suppressing the short channel effect is limited.
In addition, with the reduction in the device size, the problem concerning transportation of carriers becomes outstanding. Therefore finding ways to effectively limit the carriers and increase the carrier mobility becomes important for improving the device's drive capability.